1. Field of the Invention
The present invention relates to a synchronous Dynamic Random Access Memory (DRAM) for burst read/write operations.
2. Description of the Prior Art
FIG. 1 shows a conventional dynamic RAM (DRAM) with a conventional basic architectural configuration. FIG. 2 shows a detailed drawing of the conventional DRAM shown in FIG. 1.
In the conventional basic architectural configuration of the dynamic RAM (DRAM), as shown in FIG. 1, data read out of a memory cell selected by a word line is transferred to a sense amplifier (S/A) via a bit line.
A pair of data items amplified by the S/A are read out to an output buffer 104 through a pair of FETs 101 (shown in FIG. 2) through which the pair of data items are controlled by a signal on a column select line CSL.
In the conventional basic architectural configuration of the DRAM shown in FIGS. 1 and 2, we will describe one of architectural configurations of a conventional synchronous DRAM (SDRAM) below.
FIG. 3 shows a path of the synchronous data read/write operations for the input and output of one unit of data. These operations will now be briefly explained.
During the output of one string of serial data, when the head address of the data in the string is provided, two adjacent CSLs corresponding to column select lines CSL1 and CSL2 are selected, and four items of data from memory cells are read out through four pairs of DB lines. This is a 2-bit prefetch system whereby data read out of two columns within two clock cycles simultaneously is transferred serially, and two pairs of DB lines are selected to coincide with serial access addressing from the four pairs of DB lines. This selection is performed by a DB selector. The data on the two pairs of selected DB lines is transferred to two pairs of RWD lines RWD1 and RWD2. Data in the first two cycles on the two pairs of RWD lines are stored into registers R1 and R2, and data in the next two cycles are stored into registers R3 and R4.
In this write operation to the resisters R1 to R4, the sequence for storing the data from the RWD lines RWD1 and RWD2 in the registers R1 to R4 is determined by RWD switches RWDS1 and RWDS2.
The data passing through these switches RWDS1 and RWDS2 is stored in access sequence into the registers R1 to R4 by register transfer gates RTG1 and RTG2 which open alternately every two cycles to provide high speed data output.
The RWD switches 1, 2 and the register transfer gates RTG1 and RTG2, as shown in FIG. 3, are made up of gates of FETs. The data stored in the registers R1, R4, for example, as shown in FIG. 4, is read out to the output buffer 104.
FIG. 5 shows a timing chart of the data transfer state in this data read operation described above. In FIG. 5, the data transfer state is illustrated under the condition that the burst length is 8 and the number of latency is 3 counted after address is determined or latched.
In FIG. 5, the operational state of each of the configurational elements shown in FIG. 3 is illustrated. These will now be explained in order.
First, in a clock cycle (CLK), a Column Address Strobe (/CAS) is switched from high to the low, the head address of one string of burst data is set, and access is commenced. After the head address is determined, according to the addressing sequence of the burst data access, an internal address is produced for every two cycles and an access operation is carried out at the rise of levels of every two column select lines CSL.
When the column select line CSL rises, the DB line pair immediately enters to a busy state. When the data has been kept satisfactorily on the DB line pair, using the DB selector, data from two pairs in four-pair DB lines is transferred to the RWD line pair, and the RWD lines enter to the busy state every two cycles.
When data is kept sufficiently on the RWD lines, the data is stored into the register by the operation of one of the register transfer gates RTG1, RTG2 and one of the RWD switches RWD1 and RWD2.
In this data store operation, the RWD switches 1 or 2 are suitably selected by addressing for the burst data and turned ON, normally the register transfer gates 1 and 2 are alternately ON, and the data is stored in the register.
When the respective register transfer gates RTG1 and RTG2 are turned ON, the contents of the register are immediately rewritten and data is transferred serially from an OUTPUT which enters the busy state.
While these burst data transfer are controlled, after the access for the burst data transfer is completed, the clock cycle for commencing a new burst transfer access is restricted because the internal operation is operated in two clock cycles. In other words, a time restriction is produced so that a new access is not commenced from an optional cycle after the burst data transfer is completed. When a new burst data transfer access is commenced from an optional cycle after the previous burst data transfer is completed, it is necessary to temporarily reset the control of the clock period and commence the new burst data transfer after two clock cycles.
For this reason, a data burst completion signal is generated internally at a time when the burst data transfer access is completed and when it becomes unnecessary to control the burst data transfer access. The control system is reset from the clock cycle in which the data burst completion signal is generated. This clock cycle is designated by the reference number CLK9 shown in FIG. 5.
Because if the reset is not completed it is not possible to commence a new burst data transfer cycle and a time period of several tens of ns is required for the reset, the setting of a new starting address for a new burst data transfer occurs from a clock cycle 11. For this reason, it is not possible to set a new burst access in clock cycles CLK9 and CLK10. Accordingly, the output of a new burst data transfer is not possible after the thick dotted line in FIG. 5, so that data output of the new burst data transfer is only possible after the thin dotted line, which is disadvantageous in high speed burst data transfer.
As can be seen from the foregoing description, the reset operation described above is required in a conventional synchronous DRAM during the transfer for a burst data string. Because this reset operation takes a comparatively long time, it is very troublesome to transfer burst data continuously at high speed.
In addition, in a conventional synchronous DRAM, the data transfer system for cell arrays of multibank architectural configuration is not arranged in an optimum manner, necessitating an increase in the area of the chip.
In accordance with one aspect of the present invention, there is provided a synchronous memory, comprising:
a memory cell array having a plurality of memory cells arranged in a matrix, the memory cell array being divided into first, second, third and fourth banks arranged in a first direction, each of the banks having a plurality of memory cell arrays arranged in a second direction;
a first bus arranged between the first and the second banks for transferring data from and to the memory cell arrays in the first and the second banks;
a second bus arranged between the third and the fourth banks for transferring data from and to the memory cell arrays in the third and the fourth banks; and
an activating circuit for selectively activating memory cell arrays belonging to a single bank of the first to fourth banks so that at least two memory cell arrays within the single bank are simultaneously activated.
In the synchronous memory described above, the activating circuit activates four memory cell arrays within the single bank simultaneously, the first bus includes four I/O line pairs, and the second bus includes four I/O line pairs.
In the synchronous memory described above, the synchronous memory further comprises a peripheral circuit coupled to a plurality of I/O pads, the peripheral circuit arranged in the area between the first to fourth banks.